(1) Field of the Invention
The present invention relates to methods used to fabricate integrated circuits, and more specifically to a method used to form a gate dielectric layer for a thin film transistor.
(2) Description of Prior Art
Thin film transistors (TFT), have been used for specific integrated circuit applications. One such application for TFT devices have been in the area of liquid crystal display (LCD), panels. A transmissive-type LCD display panel comprises an array of light valves that selectively transmit incident light, in order to form an image on a display screen when the panel is backlit by a strong incandescent or fluorescent light source. Driving circuitry is provided to operate the light valves. Typically each light valve is energized by a TFT device, addressed along row and column addressing lines.
The TFT devices are comprised with a dielectric layer, used as the gate insulator layer, formed on a channel portion of an underlying active layer. For conventional metal oxide semiconductor field effect transistor (MOSFET), used for memory and logic applications, the gate insulator layer is a thin silicon dioxide layer, thermally grown on an underlying single crystalline, silicon substrate. In contrast, the gate dielectric layer used in TFT applications, is grown, or formed on an underlying active region comprised of polysilicon. Unlike single crystalline silicon, this polysilicon layer is comprised of numerous small grains which create an uneven surface. The ability to thermally grow a gate dielectric layer, with the desired integrity in terms of leakage and breakdown, is adversely influenced by the unevenness of the underlying polysilicon surface, when compared to counterpart gate dielectric layers formed on underlying single crystalline silicon surfaces. Therefore a conventional gate dielectric layer formed on this uneven polysilicon surface will give inadequate TFT parametric integrity such as low gate breakdown voltage and high gate leakage current.
The present invention will describe fabrication procedures used to improve the integrity of a gate dielectric layer, for a TFT device, formed on an underlying active layer, such as polysilicon. The present invention will feature specific growth and anneal sequences for the TFT gate dielectric layer, which have demonstrated to improve the parametric performance of the overlying gate insulator layer. The present invention will also describe a novel process sequence, used to improve the integrity of a deposited gate dielectric layer. The deposited gate dielectric layer can either be used as an overlying component of a composite gate dielectric layer, comprised of the deposited layer on the underlying thermally grown gate dielectric layer, or used as the gate dielectric layer, directly on the underlying active layer. Prior art, such as Arghavani et al, in U.S. Pat. No. 6,124,171, as well as Tai et al, in U.S. Pat. No. 6,121,095, describe methods of forming silicon dioxide gate dielectric layers on underlying single crystalline silicon substrates, however these prior arts do not describe the novel process sequence, introduced in this present invention, in which specific growth and anneal procedures are detailed for a composite gate dielectric layer, or for a thermally deposited gate dielectric layer, on an underlying, non-single crystalline, active layer.